The present invention relates generally to intra-chip high-speed serial communication for integrated circuit semiconductor devices. Specifically, the communication system may provide one or more of high-speed, high-bandwidth, low-power, and transparent intra-chip communication by utilizing Time Division Multiplexing (TDM) of signals over one or more of coaxial or Wafer Level Package (WLP) waveguides.
Serial links, so-called Serializer/Deserializers (SerDes), have already begun to replace parallel communication systems for inter-chip communications. Examples include Serial Advanced Technology Attachment (SATA) which replaces Parallel ATA (PATA), Peripheral Component Interconnect Express (PCI-e) which replaces parallel PCI (PCI-X), and Gigabit Ethernet (GbE) which replaces Fast Ethernet (100Base-T Ethernet).
There are several advantages of SerDes over parallel communication systems. SerDes utilize low-loss LC transmission lines that can yield a 10× improvement in signal rise times versus the RC interconnects utilized by parallel communication systems. SerDes is more power efficient than parallel communication systems for transmission of multi-gigabit-per-second (multi-Gbps) data signals over distances greater than several millimeters on chip at deep submicron process technology nodes. Finally, SerDes provides embedded clock information in the transmitted data stream, overcoming many of the clock skew and clock jitter limitations of multi-Gbps parallel communication systems.
Consequently, there has been much work to implement serial communication systems for intra-chip communication. These systems entail multiple SerDes communication links over standard on-chip metal-layer interconnect technology (for example Dally, “Interconnect-Centric Computing,” 2007). However, on-chip metal layer interconnect technologies suffer from high line losses that must be compensated for or managed by the communication system, resulting in one or more of unfavorable power consumption, circuit complexity, circuit gate count, and circuit area. Other on-chip communication systems have implemented standard data communication over Wafer Level Package (WLP) interconnect technology, but have not utilized SerDes methodologies (for example Carchon, “Wafer-Level Packaging Technology for Extended Global Wiring and Inductors,” 2003). WLP has similar line-loss impairments as on-chip interconnects, but to a lesser extent, due to the utilization of thicker conductor and insulator layers deposited on the wafer. The present invention implements an intra-chip communication system that shares the benefits of inter-chip SerDes systems by mitigating the drawbacks of WLP or metal-layer communication systems. Such intra-chip communication system utilizes a TDM scheduling methodology to serialize and transceive intra-chip digital data over coaxial interconnects. Such intra-chip communication system does not preclude the use of WLP interconnects; in fact, an alternate embodiment is to use WLP interconnects in place of, or along with, coaxial interconnects.
A coaxial interconnect is a transmission line comprising a central conductor surrounded by a conductive outer shield, with an insulator or gap disposed therebetween. Such total enclosure of the central conductor by the outer shield prevents electromagnetic fields from escaping the vicinity of the coaxial interconnect—similar to micro-strip, strip-line, or co-planar waveguide technologies—which results in lower crosstalk and more constant impedance. A commercially available coaxial interconnect technology is ‘microCoax,’ developed by Bridgewave Communications, Inc. of Santa Clara, Calif. (Pasternak, et. al. U.S. Pat. No. 7,520,054-B2). It has been designed and used for extremely high frequency inter-chip signal communication in the 30 to 300 GHz range, called Millimeter Wave (MMW) communication. An advantage of microCoax is that it is amenable to low-cost chip wire-bonding manufacturing techniques. microCoax, and other coaxial interconnect technologies, were neither explicitly designed for nor have been previously used for transceiving high-speed serial intra-chip signals, primarily due to the lack of a suitable, scalable, and practical intra-chip communication system, which the present invention addresses and solves.
It is well known that multi-Gbps single-system-clock-cycle (single-cycle) cross-chip communication—distances greater than a few millimeters—has become impossible. This necessitates multi-cycle Finite State Machine (FSM) design methodologies for digital logic or implementation of high-speed intra-chip communication systems capable of transceiving signals across chip within a single system clock cycle. Because multi-cycle FSMs are much more complicated than single-cycle FSMs to implement, verify, and test, and due to well established Electronic Computer-Aided Design (ECAD) models for single-cycle FSM design, single-cycle FSMs are preferred for digital logic.
Accordingly, what is desired, and has not heretofore been developed, is an intra-chip communication system that utilizes coaxial interconnects to achieve high-speed signal communication over distances greater than several millimeters. It is further desired that the intra-chip communication system be capable of transmitting and receiving such signals over such distances within a single system clock cycle, thereby being amenable to standard single-cycle FSM design methodologies. The intra-chip communication system utilizes TDM to aggregate multiple low-speed signals onto one or more high-speed coaxial interconnects using SerDes methodologies described in the following description of the invention.